A. Field of the Invention
This invention relates to those logical networks utilized in the arithmetic sections of present day data processing system known as shift matrices or barrel switches. These networks are used to accomplish high speed shifting of data in such a data processing system. More particularly it relates to a unique shift matrix design which not only simplifies shift count conversion but also includes a novel method of parity prediction for such a matrix utilizing a gated parity network.
B. Prior Art
As previously noted, the arithmetic sections of many contemporary computers utilize networks commonly referred to as shift matrices or barrel switches to accomplish rapid shifting of data. In most cases the matrix is composed of two or more ranks of multiplexers interconnected to perform the matrixing of any given bit position of a data item to any other bit position. Standard part families offer very few parts to assist in shift matrix implementation. The few parts that are available are cumbersome to control and it is difficult to implement the full generality of shifting modes required by contemporary computers.
Normally, earlier shift matrixes have been designed to shift in only one direction, either right or left, to conserve logic circuitry. Shifts in the opposite direction have usually been handled by converting the shift count to an equivalent shift in the designed direction. This has been accomplished in the past by subtracting the shift count from the design radix of the matrix. (i.e., for a 36-bit wide matrix the radix is 36, etc.). This, of course, adds timing overhead to the delay ordinarily associated with passage through the matrix.
Further, in many modern machines, increased emphasis is being placed on error detection in all data paths. The complexity of shift matrices makes this very difficult to achieve when all of the modes in which a matrix must function are considered. The simplest method, but most costly, has been to duplicate the entire matrix and compare the outputs. Parity checking, to date, has been just as costly because the networks required to predict final parity of the matrix output for the various modes, circular or open-ended shifts with zero or sign fill in either direction, usually exceeds the amount of logic circuitry required to implement the matrix.